Computer systems are made up of components that may communicate with one another for various purposes. Links that interconnect computer components may provide a mechanism for transferring data and clock signals between the components. Also, each link generally includes a plurality of lanes.
High reliability links are generally expected to function in the face of one or more lane failures (such as a clock lane failure). This may be done by repurposing a data lane as a clock lane (also referred to as clock failover). However, a repurposed data lane, when used as a clock lane, may result in marginal electrical behavior. Alternatively, some designs may utilize a redundant clock lane which is used in response to failure of a primary clock lane. Clearly, such approaches pose issues with respect to operational correctness/efficiency, additional silicon real estate requirements, and/or extra power consumption by the additional circuitry.